Job Description

Job Description – SoC Architect (Chiplet-Based Systems)
Company

Mulya Technologies

Position

SoC Architect – Chiplet-Based Systems

Location
Bangalore / Remote (Anywhere in India)
Employment Type
Full-Time
Role Overview

We are seeking an experienced SoC Architect to lead the architecture and development of next-generation chiplet-based AI systems. The role focuses on designing scalable modular compute platforms using advanced chiplet integration technologies.

The ideal candidate will drive architecture decisions for high-bandwidth memory and I/O connectivity, scalable die-to-die communication, subsystem integration, and chiplet partitioning strategies for AI accelerator platforms.

You will collaborate closely with packaging, PHY, interconnect, and verification teams to define efficient multi-die systems optimized for performance, latency, bandwidth, and power.

Key Responsibilities
Architecture & System Design
Define SoC architecture for chiplet-based AI inference platforms.
Design scalable inter-chiplet communication architectures and synchronization strategies.
Drive partitioning decisions across compute, memory, I/O, and control chiplets.
Architect coherent and low-latency communication frameworks between disaggregated subsystems.
Interconnect & Interface Design
Define high-bandwidth die-to-die interconnect requirements including:
Bandwidth
Latency
Power optimization
Work on interfaces such as:
UCIe
BoW
Custom die-to-die links
Architect PCIe and DMA interfaces for host connectivity and chiplet communication.
Memory & Subsystem Integration
Own subsystem architecture for:
PCIe Gen4/Gen5
RISC-V clusters
LPDDR4/LPDDR5
HBM memory systems
Integrate and validate third-party IPs related to memory, I/O, and inter-chip communication.
Collaboration & Verification
Collaborate with packaging and PHY teams for multi-die integration.
Support multi-chip system bring-up, validation, and debug activities.
Contribute to system-level verification and test/debug methodologies.
Required Qualifications
BS/MS/PhD in Electrical Engineering, Computer Science, or related field.
10–25+ years of experience in SoC architecture or multi-die/chiplet system design.
Strong expertise in chiplet-based architectures and packaging technologies such as:
UCIe
EMIB
Foveros
Deep understanding of:
Modular SoC partitioning
Die-to-die interconnect architectures
High-performance memory systems
Experience with:
PCIe Gen4/Gen5
RISC-V subsystems
LPDDR4/5
HBM interfaces
Familiarity with:
Chiplet-aware verification methodologies
Multi-chip bring-up and debugging
Hands-on experience with:
SystemVerilog
UVM
System-level test and debug strategies
Preferred Skills
Experience in AI accelerator architecture.
Knowledge of scalable memory hierarchy optimization.
Expertise in low-power and high-throughput system design.
Strong debugging and cross-functional collaboration skills.
Why Join?
Opportunity to work on cutting-edge AI and chiplet technologies.
High-impact role in defining next-generation compute platforms.
Flexible remote working option across India.
Exposure to advanced packaging and interconnect ecosystems.