Design Verification Engineer- AI Accelerator

Job Description

Job Description: Design Verification Engineer – AI Acceleration SoC
Company: Velaura
Job Title: Design Verification Engineer
Employment Type: Full-time
Experience: 8+ Years
Job Posted: 13 days ago
Domain: Semiconductor / Physical AI / AI Hardware
Salary: Not specified – base salary plus competitive equity compensation
Benefits: Health insurance, paid time off, and other comprehensive benefits
Job Summary
Velaura is looking for experienced Design Verification Engineers to verify its next-generation Physical AI System-on-Chip (SoC), with a particular focus on custom AI acceleration units, including matrix and vector compute engines.

The role involves working with architecture, RTL, software, and system teams to ensure the correctness, performance, reliability, and safety of hardware designs. Candidates will develop verification environments, reference models, test plans, and coverage strategies for AI accelerator hardware.
Key Responsibilities
– Own verification of custom AI acceleration units, including matrix and vector compute engines.
– Translate microarchitecture specifications into detailed test plans and coverage strategies.
– Develop verification environments using SystemVerilog, UVM, C, and C++.
– Build stimulus generators, checkers, assertions, trackers, and coverage models.
– Develop reference models for GEMM and GEMV operations and compare hardware outputs.
– Verify accelerator data flow, including operand staging, tiling, accumulation, and result writeback.
– Validate numerical precision, rounding, and quantization against architecture specifications.
– Evaluate throughput, latency, utilization, and performance per watt.
– Execute regression testing and track bugs, coverage metrics, and verification progress.
– Support emulation and pre-silicon bring-up in collaboration with compiler and runtime teams.
Required Skills & Qualifications
– 8+ years of experience in verification of high-performance computing or complex digital designs.
– Strong knowledge of LLMs, transformer architecture, and inference data flow.
– Understanding of GEMM and GEMV operations and their hardware implementation.
– Hands-on experience with:
– SystemVerilog
– UVM
– C and C++
– Assertions and coverage-driven verification
– Reference models using C, C++, or Python
– Understanding of numerical formats and precision trade-offs, including FP16, BF16, FP8, and INT8.
– Ability to independently own block-level verification from test planning through coverage closure.
– Strong debugging and complex failure analysis skills.
– Bachelor’s degree or higher in:
– Computer Engineering
– Electrical Engineering
– Computer Science
Preferred Qualifications
– Experience porting LLM or neural network models to RTL and verifying them.
– Experience verifying custom AI accelerators developed from scratch.
– Familiarity with systolic arrays, tensor cores, attention mechanisms, KV cache, or Mixture of Experts (MoE) hardware.
– Experience with PyTorch, ONNX, or accelerator compiler/runtime stacks.
– Knowledge of formal verification, gate-level simulation, or silicon bring-up.
– Exposure to performance modelling, power analysis, profiling, and workload characterization.
– Familiarity with robotics, drones, autonomous vehicles, or edge AI systems.
– Experience using AI-assisted verification workflows.
Compensation & Benefits
– Competitive base salary.
– Equity compensation.
– Medical, dental, and vision coverage may be included.
– Health insurance.
– Paid time off.
– Flexible work arrangements.
– Professional development opportunities.
Actual compensation will depend on skills, qualifications, experience, and geographic location.
About Velaura
Velaura develops next-generation compute technology for cloud, edge, and Physical AI applications. Its solutions aim to power robots, autonomous systems, drones, and other intelligent machines through efficient computing technology.
Application / Contact Details
Email: careers@velaura.ai