DFT Architect

Job Description

Hiring: DFT Architect | ASIC / SoC

🏢 Company: EnchargeAI
📍 Location: (add location if applicable)
💼 Role: DFT Architect

🧩 Role Overview

We are looking for an experienced DFT Architect to lead Design-for-Test (DFT) architecture, implementation, and verification for complex ASIC/SoC designs.

This role involves working across MBIST, LBIST, ATPG, and silicon bring-up, collaborating closely with design and physical design teams.

🔧 Key Responsibilities
Design MBIST & LBIST logic using SystemVerilog / Verilog
Implement and verify DFT architectures:
EDT, LBIST, SSN
MBIST, IJTAG
IEEE 1149.1 / 1149.6
Perform ATPG, coverage analysis, and simulations (VCS / Questa – unit & SDF level)
Execute DFT insertion for embedded blocks in SoCs
Handle end-to-end DFT implementation for SoC designs
Insert and verify DFT logic using Cadence Modus
Collaborate with Physical Design (PD) teams for timing closure
Define silicon bring-up strategy and validation plans
🎯 Required Skills
Strong experience with Siemens / Mentor DFT tools
Hands-on expertise in DFT insertion for embedded SoC blocks
Proficiency in:
Makefile
TCL
Python (for automation)
Solid understanding of ASIC/SoC test methodologies
🤝 Contact

📧 Supriya Sharma – Supriya@mulyatech.com