Job Overview
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Expiration date
October 31, 2026
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Job Description
Location: Bangalore / Remote (Anywhere in India)
🏢 Company: EnCharge AI
Role Overview
We are looking for an experienced DFT Architect to lead design-for-test strategies and implementation for complex SoC/ASIC designs. The ideal candidate will have deep expertise in DFT architecture, ATPG, and silicon bring-up.
Key Responsibilities
Design and implement MBIST & LBIST logic using SystemVerilog/Verilog
Develop and verify DFT architectures including:
EDT, LBIST, SSN, MBIST
IJTAG, IEEE 1149.1, IEEE 1149.6
Perform ATPG, analyze fault coverage, and debug low coverage issues
Simulate DFT structures and patterns using tools like VCS and Questa (unit & SDF level)
Execute test insertion for embedded blocks within SoC
Work on block-level and chip-level DFT verification
Use Cadence Modus for DFT insertion and validation
Collaborate with Physical Design teams to close timing on post-layout netlists
Perform silicon bring-up planning and execution strategy
Automate DFT flows using Makefile, TCL, and Python
Required Skills & Qualifications
Strong experience with Siemens/Mentor DFT tools for SoC test insertion
Hands-on expertise in ATPG, MBIST, LBIST, IJTAG
Experience with Cadence Modus
Proficiency in:
SystemVerilog / Verilog
Makefile, TCL, Python
Strong debugging and fault analysis skills
Experience working with cross-functional teams (PD, design, validation)
Nice to Have
Experience in post-silicon validation / bring-up
Exposure to large-scale SoC architectures
Knowledge of advanced DFT compression techniques
Contact / Apply
📧 Supriya Sharma
✉️ supriya@mulyatech.com
