DFT Architect

Job Description

Hiring: DFT Architect | ASIC / SoC

🏢 Company: EnchargeAI
📍 Location: Bangalore / Remote (Anywhere in India)
💼 Role: DFT Architect

🧩 Role Overview

We are looking for a skilled DFT Architect to lead Design-for-Test architecture, implementation, and validation for complex ASIC/SoC designs.

This role involves hands-on work across MBIST, LBIST, ATPG, and silicon bring-up, collaborating with design and physical design teams.

🔧 Key Responsibilities
Design MBIST & LBIST logic using SystemVerilog / Verilog
Implement and verify DFT architectures:
EDT, LBIST, SSN
MBIST, IJTAG
IEEE 1149.1 / 1149.6
Perform ATPG runs, coverage analysis, and debugging
Simulate using VCS & Questa (unit and SDF level)
Execute DFT insertion for embedded blocks in SoCs
Work on end-to-end DFT implementation at block & chip level
Perform:
Fault coverage analysis
Root-cause analysis for low coverage
Verify ATPG & MBIST patterns
Collaborate with Physical Design (PD) teams for timing closure
Define silicon bring-up strategy and validation plans
🛠️ Tools & Technologies
Siemens / Mentor DFT tools
Cadence Modus
Simulation: VCS, Questa
Scripting & automation:
Makefile
TCL
Python
🎯 Requirements
Strong experience in DFT architecture & SoC test methodologies
Hands-on expertise in ATPG, MBIST, LBIST, IJTAG
Experience with embedded block test insertion
Solid debugging and coverage analysis skills
Ability to work in complex ASIC/SoC environments
📩 Contact

📧 Supriya Sharma – Supriya@mulyatech.com